This invention relates to semiconductor devices and, more particularly, to self-aligned contacts in complementary-field-effect-type (CMOS) circuits such as memory circuits and to a method for making those self-aligned contacts.
Integrated memory circuits comprise at least two parts, the memory cell array and the peripheral circuitry. In integrated CMOS memory circuits, the array of memory cells is generally constructed using NMOS field-effect transistors because of the speed advantage over PMOS field-effect transistors, which are included in the peripheral circuitry. The diffusion contact for each memory cell accounts for a significant percentage of the cell area both because of the required contact size and because of the required diffusion-overlap for the contact. One method to reduce the cell area is to use a diffusion contact that is self-aligned to the field-oxide edge.
Because of the presence of PMOS contacts in the peripheral circuitry, an extra contact mask has heretofore been needed to form a diffusion contact that is self-aligned to the field-oxide edge. Adding the extra mask has two disadvantages. One of those disadvantages is an increase in wafer process cost. The other disadvantage is that the extra mask exposes already-formed contacts to the resist process, making it more difficult to produce clean contacts than when using a standard single-mask contact process.